1. Field of the Invention
The present invention relates to an apparatus for compensating for an error of a time-to-digital converter (TDC) capable of compensating for an error caused by a delay included in the TDC through a digital arithmetical operation scheme and simply changing the time resolution of the TDC by changing a digital control value without having to alter a device design.
2. Description of the Related Art
A time-to-digital converter (TDC) is used to measure a time difference between a reference signal and a comparison signal. Recently, the TDC is used in an all-digital phase locked loop in which a signal voltage is based on a signal period or phase, rather than a reference measurement.
FIG. 1 illustrates the related art TDC having a single delay line.
The TDC 100 includes a delay 110 including a plurality of delays 111 to 116 for delaying a first input by a delay phase (ΦΔt) to generate a plurality of delay signals, a reference line 120 for transferring a second input, flip-flops 130 for acquiring each value of the plurality of delay signals in synchronization with a rising edge or a falling edge of the second input transferred through the reference line 120, and an encoder 150 for recognizing how many delays the first input has passed through based on output values from the flip-flops 130 and providing corresponding information.
Each of the plurality of delays 111 to 116 may be implemented as an inverter, buffer, resistor, and the like, and the delay phase (ΦΔt) provided from the delays determines a time resolution value of the TDC 100. Thus, in order to accurately compare the first and second inputs, the delay phase (ΦΔt) must be fragmented to enhance time resolution of the delays.
FIG. 2 illustrates another related art TDC including Vernier delay lines.
Unlike the TDC 100 of FIG. 1, in the TDC 200 of FIG. 2, a reference line 220 includes a plurality of delays (i.e., delay chains 221 to 226) as a delay line 210 does.
In this case, delay times of a plurality of delays 211 to 216 for delaying the first input and that of the plurality of delay chains 221 to 226 for delaying the second input are different, and such differences between the delay times determines a time resolution of the TDC. For example, if the delay chains 211 to 216 included in the delay line 210 have a delay time of 20 picoseconds while the delay chains 221 to 226 included in the reference line 220 have a delay of 30 picoseconds, the TDC 200 would have a time resolution of 10 picoseconds.
The TDC 200 including the Vernier delay line as illustrated in FIG. 2 has advantageously high time resolution when compared with the TDC 100 of FIG. 1.
However, the TDC 200 has a difficulty in that the delay line 210 to which the first input is transferred and the reference line 220 to which the second input is transferred must be accurately synchronized.
In addition, compared with the TDC 100 of FIG. 1, because the TDC 200 in FIG. 2 performs a time-to-digital conversion operation with the small time resolution, it takes time to measure the interval between the signal of the first input and that of the second input, the hardware size increases, and much power is consumed.